Ci-STEM Journal of
Advanced Materials and Computing

This paper discusses the design and implementation of a globally asynchronous, locally synchronous (GALS) 8051 microcontroller with low power consumption and accurate time management for embedded applications. Unlike the traditional 8051 architecture, the proposed design divides the circuit into two local clock domains, thus eliminating the need for a global clock to synchronize the entire circuit and reducing unnecessary clock skew problems and switching requirements. An asynchronous interface technique is implemented in this proposed design to facilitate reliable communication between clock domains, along with incorporating power-aware methodologies, such as selective activation of blocks and clock gating techniques, to make the circuit power efficient. The complete microcontroller circuit, comprising fetch, decode, and execution stages, was designed using Verilog HDL language and synthesized with the help of Genius software from Cadence using GPDK 90 nm technology. A simulation technique was applied to validate the functionality of the design, and its performance was analyzed based on the area, power consumption, and time delays.
Key Words: GALS, 8051-inspired microcontroller, dual-clock architecture, asynchronous handshake, clock domain crossing, power-aware architecture, Internet of Things applications.
Citation: Rajakumari. A. et al, “Instruction-Level GALS Architecture for Low-Power 8051-Compatible Embedded Systems,” Ci-STEM Journal of Advanced Materials and Computing, Vol. 1(2), pp. 45-57, 2026.

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Practical quantum computation requires logical operations whose error rates lie many orders of magnitude below those of any physical qubit. Quantum error correction (QEC) only closes that gap if physical noise is weak enough, uncorrelated enough and decoded fast enough. We provide a critical, structured review of the physical mechanisms limiting the stability of qubits, the mathematical foundations of QEC, the main code families, and the experimental record on superconducting, trapped-ion, neutral-atom, semiconductor-spin, photonic, bosonic and topological platforms. Reproducible circuit-level simulation of rotated surface-code memories (Stim and PyMatching, fixed seeds, uniform depolarizing noise) places the threshold crossing near 0.75% and yields a suppression factor consistent with a slope-based parameter near 1%. We find that the logical failure probability changes by at most 16 % for a decoder-calibration study with a global mismatch between assumed and true error rates, while discarding noise information increases it by a factor 1.5-2.0. Published experiments analyzed include distance-7 superconducting memories with a suppression factor of 2.14 ± 0.02 per distance step, neutral-atom logical-processor demonstrations and bosonic memories beyond break-even. We enumerate seven testable research proposals and gaps in correlated noise, leakage, real-time decoding, non-Clifford cost, and cross-platform benchmarking. We intentionally do not include commercial timelines.
Key Words: decoherence, fault-tolerant quantum computing, logical qubits, quantum error correction, qubit stability, quantum LDPC codes, surface code.
Citation: P. Yakaiah. et al, “A study on Qubit Stability, Quantum Error Correction and Performance Limitations,” Ci-STEM Journal of Advanced Materials and Computing, Vol. 1(2), pp. 58-78, 2026, doi: 10.55306/CJAMC.2026.010202

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The growing use of wearable sensors and real-time monitoring systems has increased the need to have real-time healthcare analytics based on bio-signals like ECG, EEG, and EMG. Nevertheless, traditional cloud-based and fixed AI architectures are characterized by high latency, energy inefficiency, and non-adaptability to the different complexities of physiological signals. The research gap is critical in that there is no existing dynamic, low-power architecture of AI chip that can dynamically adjust computational resources according to real-time bio-signal features. To solve this, a Bio-Signal Driven Adaptive AI Chip Architecture (BDAAIC) is suggested, which incorporates the neuromorphic processing, dynamic resource allocation and signal-aware model reconfiguration. The structure comprises bio-signal complexity analyzer, adaptive neural processing unit and real-time reconfiguration controller. The benchmark datasets such as MIT-BIH Arrhythmia and PhysioNet EEG datasets are used in experiments under edge computing conditions. The suggested architecture reduces the accuracy, latency, and enhances energy efficiency by 97.36, 28, and 32 percent, respectively, over the traditional AI-based healthcare systems. The findings indicate the usefulness of adaptive hardware intelligence in facilitating real-time, scalable, and energy-efficient healthcare analytics.
Key Words: Adaptive AI Chip, Bio-Signal Processing, Edge AI, Neuromorphic Computing, Physiological Signal Analysis. Real-Time Healthcare.
Citation: Jayashree. P et al., “Emerging Computing Strategies in VLSI: A Comprehensive Review of Device, Architecture, and Beyond-CMOS Paradigms” Ci-STEM Journal of Advanced Materials and Computing, Vol. 1(2), pp. 79-87, 2026, doi: 10.55306/CJAMC.2026.010203

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In a battery electric vehicle, every watt of power wasted by the power converters is a watt lost from range, charging speed and cooling headroom. Silicon carbide (SiC) and gallium nitride (GaN) power devices reduce those losses and allow higher switching frequencies than silicon, but they do so with different device physics and different packaging problems. The study is comparative and analytical, and no new experiments were conducted. We compare vertical 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) with lateral enhancement-mode AlGaN/GaN high-electron-mobility transistors (HEMTs). We correlate drift-region and two-dimensional-electron-gas design to blocking voltage and on-state resistance. Then, a loss and junction-temperature framework is applied to two manufacturer datasheets, a 1200V SiC MOSFET and a 600V GaN HEMT, with different ratings and test conditions are provided with explicitly specified. A first-order analytical model puts the frequency at which switching loss overtakes conduction loss near 43 kHz for the SiC example and near 74 kHz for the GaN example, whose switching energy is estimated rather than measured. A sourced timeline shows how each technology reached vehicle-relevant ratings. Published work on traction inverters, onboard chargers, DC–DC converters, and auxiliary stages points to SiC for high-current inverters and 800V systems, and to GaN for compact, high-frequency stages at 650V and below. The major trade-offs are gate-oxide stability, short-circuit capability, dynamic on-resistance, package inductance and automotive qualification. We enumerated the research gaps they create.
Key Words: electric vehicles, gallium nitride, high-frequency converters, power electronics, power MOSFETs, wide-bandgap semiconductors, silicon carbide.
Citation: C. R. Rao et al., “Design of Silicon Carbide and Gallium Nitride Power Devices for Electric Vehicle Applications” Ci-STEM Journal of Journal of Advanced Materials and Computing, Vol. 1(2), pp. 88-99, 2026, doi: 10.55306/CJAMC.2026.010204

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